As the dimensions of semiconductor devices continue to shrink, various issues arise, imposing increasing demands for methodology enabling the fabrication of semiconductor devices having high reliability and high circuit speed. For example, smaller transistors allow more transistors to be placed on a single substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area. However, semiconductor devices typically require reduced feature sizes. For example, as the gate width for transistors decreases, the gate dielectric thickness decreases as well. The decrease in gate oxide thickness is driven in part by the demands of overall device scaling. As gate conductor widths decrease, for example, other device dimensions including layer thicknesses must also decrease in order to maintain proper device operation. As the thickness of the underlying layer is reduced, it becomes increasingly important to minimize material consumption.
Nickel silicide (NiSi) or nickel germanide (NiGe) is formed on active layers to reduce contact resistance. In forming the NiSi or NiGe, part of the underlying material, silicon germanium (SiGe) or germanium (Ge), is consumed. In the manufacture of small scale products, consumption during silicidation and germanidation can degrade the junction profile, since the dopants are pushed down in the layer(s) during the manufacturing process. In addition, when dealing with small scale products, such material consumption can also result in the silicide and germanide extending deeper into the SiGe or Ge than the junction. Thus, as the thickness of the underlying layer is reduced, it becomes increasingly important to minimize material consumption.
In current processes, NiSi is axiotaxially formed on silicon (Si), which can cause thermal instabilities. Such thermal instabilities can be prevented or reduced by the addition of platinum (Pt) to the NiSi. Pt addition can also suppress the Si rich phase formation. NiGe, as formed on Ge or SiGe, however, typically does not offer axiotaxy issues. Furthermore, NiGe formation is a continuous transformation from a mixture of Ni5Ge3 and NiGe phases into NiGe at as low temperatures as >200° C., whereas NiSi forms at >300° C. after the metal rich phase and continues into a Si rich phase with increased temperatures >700° C. in a stepwise fashion.
Ge, however, typically lacks a stable oxide. As such, both aqueous and acidic chemistries attack the silicide and/or germanide during unreacted metal removal processes. In addition, SiGe or Ge consumption during silicidation and germanidation cannot be avoided if Ni is deposited and then annealed on these materials. Also, since NiGe has a lower activation energy of agglomeration than NiSi, NiGe is more susceptible to back-end-of-line (BEOL) annealing processes.
Referring to FIG. 1A through 1C, a current blanket process, for example, to form a germanide, is illustrated for simplicity. In FIG. 1A, Ni/Pt 104 is sputtered on a Ge layer 102, such as by physical vapor deposition (PVD). Then, in FIG. 1B, a rapid thermal anneal (RTA) is performed to form rich NiGe 106 on the layer 102. Subsequently, excess and un-reacted Ni/Pt 108 is stripped, for example with strong acid mixtures such as piranha (a mixture of sulfuric acid and hydrogen peroxide (SPM)) or nitric acid (HNO3) in a sink bath process, typically followed by a second RTA process to transform the metal rich phases into a low resistance NiGe layer 106. However, after the second RTA, concentrated Aqua Regia (1:4) (HNO3 plus hydrochloric acid (4HCl)) or a hot SPM, for example, at temperatures greater than 160° C., must be employed to remove the Pt residuals. However, as illustrated in FIG. 1C, during such process, the NiGe layer 106 is typically attacked, as illustrated by NiGe layer 110, and the un-reacted metal, such as un-reacted Pt or Ni 112, is typically not completely removed.
To avoid having to remove NiSi from regions other than source/drain regions, self-aligned contacts (SACs), or trench silicides, may be used. Referring to FIGS. 2A through 2F, a current process utilizing NiPt in SACs or trench silicides is described, with reference to the above described process. In FIG. 2A, an interlayer dielectric (ILD) 204, such as silicon dioxide (SiO2), is formed on an active layer 202, such as of Ge or SiGe, for example at a source/drain region. In FIG. 2B, a contact etch process is performed in the ILD 204 to form a trench 210 therein having sides 208 formed by portions of the ILD 204. Then, as illustrated in FIG. 2C, nickel platinum (NiPt) (with 5, 10, 15% or higher Pt, for example) is sputtered and deposited, as by radio frequency physical vapor deposition (RFPVD), on ILD 204 and within the trench 210, forming the NiPt layer 212.
A first RTA process is performed, such as by a microwave, flash, or laser anneal process, followed a first strip process for removal of residues, followed by a second RTA process, and a second strip process for residue removal. The process results in the structure of FIG. 2D, having a silicide 213 formed in the active layer 202 at the bottom of trench 210, with an oxide layer 214 formed over silicide 213. Adverting to FIG. 2E, a sputter cleaning process, such as an argon (Ar) sputter cleaning process, is performed to remove the oxide 214 and any further residue, followed by deposition of a liner 216 covering the sides 208, ILD 204, and top of the silicide 213. As illustrated in FIG. 2F, metal 218, e.g. tungsten (W), is deposited, filling the trench 210 and covering the metal liner 216 formed over the ILD 204.
Referring to FIGS. 3A through 3G, an alternative process to that of FIGS. 2A through 2F is described. In FIG. 3A, an ILD layer 304, such as SiO2, is formed on an active layer 302, such as of Ge or SiGe, for example. In FIG. 3B, the ILD 304 is etched to form a trench 308 having sides 306. Then, in FIG. 3C, RFPVD is performed to sputter and deposit NiPt (5, 10, 15% or higher Pt, for example) on the active layer 302 within the trench 308 on sides 306 and on ILD 304, forming the NiPt layer 310.
Continuing with reference to FIG. 3D, a first RTA process is performed, such as by a microwave, flash, or laser anneal process. Unlike the process of FIGS. 2A through 2F, a strip process is not performed. Instead, a silicide 312 is formed in the active layer 302 at the bottom of the trench, with an oxide layer 315 over the silicide 312, and the remaining metal forms a liner 314 covering the sides 306 and ILD 304. In FIG. 3E, a pre-clean process, such as an Ar sputter cleaning process, is performed to remove oxide layer 315. Then, as illustrated in FIG. 3F, metal 316, such as W is deposited over ILD 304 and in trench 308. In FIG. 3G, a chemical-mechanical polishing (CMP) process is performed down to ILD 304 to remove the metal 316 and the liner 314 above trench 308 and ILD 304, respectively, resulting in the structure of FIG. 3G.
Additionally, it is known that thermal stability of NiGe films formed on Ge or SiGe can be improved from 450° C. to 550° C. by adding an ultrathin (˜1 nm) Ti layer during Ni deposition, either as an intermediate layer between Ni and Ge or as a capping layer on Ni, such as by the formation of a ternary Ni1-xTixGe phase near the NiGe surface, which suppresses agglomeration of the underlying NiGe film. However, this process, while possibly improving thermal stability of NiGe, does not address problems related to unreacted metal in the strip processes and underlying material consumption.
A need therefore exists for methodology enabling formation of NiGe or NiSiGe with reduced Ge or SiGe consumption, and the resulting product.